IBM has achieved a remarkable milestone with its latest computer chip, measuring just 10mm x 15mm and boasting an astonishing 100 billion transistors—nearly double the count of its most advanced predecessors. This innovative chip leverages cutting-edge three-dimensional technology and offers an impressive 70% increase in energy efficiency along with 50% more power than current leading chips, paving the way for potential commercial use in the next decade.
Traditionally, chip manufacturing processes were identified by the size of individual transistors measured in nanometers, with smaller sizes typically equating to better performance. Denser components can achieve faster calculations and reduced energy consumption. However, recent trends show that sizing nomenclature, such as IBM’s “0.7 nanometers,” no longer accurately reflects the physical realities of modern chips.
According to Fu Eimei at IBM, the key advancement from the last 15 years has been the innovative approach of layering silicon chips, effectively making electrical connections while managing heat and ensuring mass-production feasibility. Bu explains that the industry has historically focused on scaling transistors horizontally. For the first time, it is now exploring depth-based scaling.
While exact measurements of this new technology’s components aren’t disclosed, it appears to be a dual-layer version of the first effective 2-nanometer chip announced by IBM in 2021, which is already seeing adoption by various top chip manufacturers, including features likely to appear in future devices like the next Apple iPhone.
The complexity and cost of developing new chip technologies have led the industry to collaboratively establish a roadmap for future innovations, coordinated by organizations like the IMEC. Although IBM’s 0.7-nanometer chip technology remains in the testing phase, it signifies a crucial step forward in global chip manufacturing, inspiring other companies to adapt.
Bu anticipates that the newly developed 0.7-nanometer chips will enter commercial devices in the next ten years. However, they will face increasing challenges, as advancements must overcome fundamental physical laws to manage quantum effects, current leakage, and other obstacles at such minuscule scales, with current chips being as thin as 15 silicon atoms.
Owen Guy, a researcher at Swansea University, points out that competitor chipmakers touting high transistor densities often utilize multiple silicon layers separated by thick substrate, which hinders true 3D architecture and complicates cooling. He emphasizes that significant downsizing of components doesn’t necessarily lead to smaller devices; the focus is primarily on enhancing energy efficiency and extending battery life for mobile devices.
A critical opportunity lies in integrating IBM’s advanced chip technology into existing global manufacturing processes. These chips are crafted in batches on 300-millimeter silicon wafers, which contain trillions of transistors, posing significant challenges for adding new features like the additional silicon layer, as complex manufacturing operations are required.
Some innovators aim to develop even smaller 0.2 nanometer technologies, where circuit components might reach atomic widths. Guy notes, “The ultimate limit is one electron and one atom. By around 2050, we may need to utilize quantum technology to facilitate the next major progress.”
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Source: www.newscientist.com